FIG. 1 illustrates different power modes for a data processing device. When an external power supply (VCCX) is available, the device operates in Normal power mode. In Normal power mode, all circuit blocks are powered and their inputs and outputs are well defined. Thus, the Normal power domain comprises all circuit blocks in the drawing. Auto-Store power mode is entered when VCCX (external power supply) drops below a specified threshold. In Auto-Store power mode, device power is derived from a backup supply (VCAP) utilizing one or more capacitors. In Auto-Store mode, circuit blocks powered by VCCX (blocks within dashed line boundaries in FIG. 1) have undefined outputs. This includes most if not all I/O circuits 102 of the device. Thus, the Auto-Store power domain comprises all circuit blocks not within dashed boundaries in the drawing, including microcontroller (uC 110), memory 108, isolation block 104, and power supply switch 107. In Auto-Store power mode, signals crossing from the Normal power domain into the Auto-Store power domain are isolated by a control signal to the isolation block 104, the signal generated by the power supply switch 107. The power switch 107 monitors VCCX and generates the control signal based on whether VCCX is above or below a specified threshold. The control signal is applied to isolation block 104 to isolate signals crossing from the Normal to the Auto-Store power domains.
A third power mode, called Sleep power mode, involves putting the device into a very low power consumption state. In Sleep power mode, all circuit blocks except those required for ‘waking up’ (transitioning out of Sleep power mode) are unpowered. VCCX powers the few circuit blocks needed to wake up from Sleep power mode.
In order to implement a Sleep power mode in a device including both Normal and Auto-Store power modes, there must exist a mechanism to reliably transition out of Sleep power mode. However, in some devices, such as those utilizing low power nvSRAMs (non-volatile static random access memories), there are no circuits which can be relied upon to power the data retention and isolation blocks between power domains while waking up from Sleep mode, in the event VCCX fails during wakeup before VCAP is sufficiently charged.
In the following description, examples are used that include nvSRAMs. Although useful to devices including nvSRAMs, the logic and techniques described herein are not limited to such devices.